1. Field of the Invention
The present invention relates to a synchronous semiconductor memory device which takes in external signals including an external control signal, an address signal, write data and the like in synchronization with a clock signal formed of a series of pulses, and more particularly, it relates to a structure for easily making a test for deciding defectiveness/nondefectiveness of memory cells at a high speed.
2. Description of the Background Art
The operating speed of a microprocessor (MPU) has been increased in recent years. On the other hand, a dynamic random access memory (hereinafter referred to as DRAM) which is employed as a main memory cannot follow the MPU in operating speed although its operation has also been speeded up. Thus, it is frequently pointed out that access and cycle times of such a DRAM bottleneck the operation of the overall system, to deteriorate its performance.
In order to improve performance of such a system, frequently employed is a technique of arranging a high-speed memory called a cache memory, which is formed of a high-speed static random access memory (hereinafter referred to as SRAM) between a DRAM and an MPU. This high-speed cache memory is adapted to store frequently-used data, and accessed when the cache stores data required by the MPU. The DRAM is accessed only when the cache memory stores no data required by the MPU. Due to the high-speed cache memory storing frequently-used data, it is possible to extremely reduce frequency of access to the DRAM, thereby eliminating influences by the access and cycle times of the DRAM and improving performance of the system.
However, the SRAM is so high-priced, as compared with the DRAM, that the method employing a cache memory is unsuitable for a relatively low-priced device such as a personal computer. Thus, awaited is improvement in performance of such a system with a low-priced DRAM.
A synchronous DRAM (hereinafter referred to as SDRAM) which operates in synchronization with a high-speed external clock signal such as a system clock signal, for example, is proposed at present as one of DRAMs operating at high speeds. JEDEC (Joint Electron Device Engineering Council) of the U.S.A. employs such an SDRAM as a main memory for a high-speed MPU, and is now in operation for standardizing the specification thereof. While the standard specification is not yet clarified in detail, the following structure is proposed at present:
(1) The SDRAM is synchronized with a clock signal having a cycle of 10 to 15 ns (nanoseconds).
(2) The first data is randomly accessed with 4 to 6 clock delay after a row address signal is inputted. Thereafter data of continuous addresses can be accessed every clock.
(3) Circuits provided in a chip are pipeline-driven while serial input/output buffers are provided in a data input/output portion to reduce an access time.
However, the aforementioned structure is a mere proposal, and no means for implementing this structure is described specifically.
On the other hand, another proposal has also been made as to provision of a test mode for deciding defectiveness/nondefectiveness of the SDRAM. As to a method of and a structure for carrying out such a test, however, no definition is made specifically.